• Y. A. Durrani Department of Electronic Engineering, University of Engineering and Technology, Taxila, Pakistan


Multiplication is the basic operation in most arithmetic features in computing systems. Generally multiplier occupies large area, long delay and high power dissipation. Therefore, low power multiplier design has been an important part in very large scale integrated (VLSI) design. Power consumption is directly related to data switching patterns and it is difficult to consider high-level application-specific data characteristics in power optimization. In this paper, we present a feasible method of pipelined array multiplier and evaluated the results by the flexible estimation methods at register transfer level (RTL). The multiplier architecture is for low power and high speed applications. The experimental results indicate that the internal optimization using pipelined technique reduces the power consumption of the circuit considerably.


Y. Oowaki et al., IEEE J. Solid-State Circuits

, No. 5 (1987).

R. Sharma et al., IEEE J. Solid-State Circuits

, No. 4 (1989).

G. Goto, et. al., IEEE J. Solid-State Circuits

, No. 9 (1992).

N. Itoh et. al., IEEE J. Solid-State Circuits 36,

No. 2 (2001) 249.

V.G. Oklobdzija, D. Villeger and S.S. Lui,

IEEE Trans. Compt. 45, No. 3 (1996) 249.

Dumitru and R. Nouta, VHDL model of an

array-of-array multiplier implemented in

CMOS Sea-of-Gates, IEEE Solid-State

Circuits Conference (1995) pp. 358-361.

K.-S. Chong, B.H. Gwee and J.S. Chang, IET

Circuit Devices System 1, No. 2 (2007) 170.

P. Chan-Ho, C. Byung-soo, L. Dong-ik and

C. Hon-Yong, Asynchronous Array Multiplier

with an Asymmetric Parallel Array Structure,

Advanced Research in VLSI (2001) 202.

A. Asati and Chandrashekhar, A High Speed

Hierarchical 16x16 Array of Array Multiplier

Design, International Conference on

Multimedia, Signal Processing and

Communication Technologies (2009) pp.


V. Tiwari, S. Malik and P. Ashar, CAD of

Integrated Circuits and Systems 17, No. 10

(1998) 1051.

C. Tsai et al., A Low Power-Delay-Product

Multiplier with Dynamic Operand Exchange,

IEEE Asia-Pacific Conference on ASICs

(2000) pp. 501-504.

Huang, et al., IEEE International Symposium

on Circuit & Systems (2002) pp. 489-492.

S. Kim and M.C. Papaefthymiou,

Reconfigurable Low Energy Multiplier for

Multimedia System Design, Proceedings of

IEEE Computer Society Workshop on VLSI


Y. A. Durrani, A. Abril and T. Riesgo, Efficient

Power Macromodeling Technique for IPBased Digital System. Proceedings for IEEE

International Symposium on Circuits &

Systems (May, 2007) pp.1145-1148.

Y. A. Durrani and T. Riesgo, Journal of Low

Power Electronics 3, No. 3 (2007) 271.

Y. A. Durrani and T. Riesgo, Elsevier Journal

of Digital Signal Processing 19, No. 2 (2009)




How to Cite

Y. A. Durrani, “HIGH-LEVEL POWER OPTIMIZATION FOR ARRAY MULTIPLIERS”, The Nucleus, vol. 50, no. 4, pp. 351–358, Nov. 2013.