• Y. A. Durrani Department of Electronic Engineering, University of Engineering and Technology, Taxila, Pakistan


Power dissipation of very large scale integrated circuits (VLSI) has emerged as a significant constraint on the semiconductor industry. For the dynamic power the voltage, capacitance and frequency are the major components of the power dissipation. In this paper, we propose a new power macromodeling technique for the power estimation of conventional metal-oxide- semiconductor (MOS) transistors. As the dynamic power is directly linked with the load capacitance (CL), it is also a lumped capacitance of all internal parasitic capacitances. In our proposed model, we take an account of the parasitic capacitances with their dependence on channel width and the length. Suitable values of other factors (i.e. threshold voltage VT, gate voltage VGS, drain voltage VDD etc.) are used for the power consumption of the MOS transistors. The Preliminary results are effective and our macromodel provides the accurate power estimation.


G. Consentino and G. Ardita, A Simplified

and Approximate Power MOSFET Intrinsic

Capacitance Simulation: Theoretical Studies,

Measures and Comparisons, Proc. of IEEE

Int. Sym. on Industrial Electronics, (2009) pp.


S. Ekbote et al., Test Structure Design,

Extraction and Impact Study of FEOL

Capacitance Parameters in Advanced 45nm

Technology, ICMTS (2009) pp. 226-230.

V. D. Kunz, T. Uchino, C. H. Groot,

P. Ashburn, D. C. Donaghy, S. Hall, Y. Wang

and P. L. F. Hemment, IEEE Transactions on

Electron Devices 50 (2003) 1487.

F. Pregaldiny, C. Lallement and D. Mathiot,

Solid-State Electron 46 (2002) 2191.

H. Kamchouchi and A. Zaky, IEEE Trans.

Electron Devices ED-30 (1983) 183.

R. Shrivastava and K. Fitzpatrick, IEEE

Trans. Electron Devices ED-29 (1982) 1870.

K. Suzuki, IEEE Trans. Electron Devices 46

(1999) 1895.

N. R. Mohaputra, M. P. Desai, S. G.

Narendra and V. R. Rao, IEEE Trans.

Electron Devices 50 (2003) 959.

E. Sicard and S. D. Bendhia, Basics of

CMOS Cell Design, Mc-Graw-Hill, ISBN

-07-150906-2 (2007).

Y. A. Durrani and S. Shahbaz, Power

Macromodelling for SRAM Cell using 0.12um

Technology, Proceedings for 3rd Symposium

on Engineering Sciences (March 2010) pp.


Y.A. Durrani and B. Arif, Power

Macromodelling for DRAM Cell using 0.12um

Technology, Proceedings for 3rd Symposium

on Engineering Sciences (March 2010) pp.


J. M. Rabaey and M. Pedram, Low Power

Design Methodologies, Kluwer Academic

Publisher, Inc. (1996).

J. Frenkil, Issues and Directions in Low

Power Design Tools: An Industry

Perspective, Proceeding of International

Symposium on Low Power Electronic Design

(1997) p. 152.

A. P. Chandrakasan, S. Sheng and R. W.

Brodersen, IEEE Journal of Solid-State

Circuit 27, No. 4. (1992) 473.

J. M. Rabaey, A. Chandrakasan and B.

Nikolic , Digital Integrated Circuit, 2nd Ed.,

Prentice Hall Publisher (2003).

Albert Z.H. Wang, On Chip ESO Protection

for Integrated Circuits, An IC Design

Perspective, Kluwer Academic Publishers,

ISBN 0-7923-7647-1 (2002).

X. Chen and D. Velencies, I.R.E.E 1, No. 123

(2006) 513




How to Cite

Y. A. Durrani, “ACCURATE POWER ANALYSIS FOR CONVENTIONAL MOS TRANSISTORS USING 0.12µm TECHNOLOGY”, The Nucleus, vol. 50, no. 4, pp. 341–350, Nov. 2013.